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BCM5632
PRODUCT
(R)
Brief
OF BENEFITS
12 GIGABIT + 1 10-GIGABIT SWITCHING PROCESSOR
BCM5632 FEATURES SUMMARY
* Supports 12 Gigabit ports and one 10-Gigabit uplink in wirespeed operation * Gigabit ports support TBI (1000BASE-X) or GMII (1000BASE-T) interfaces * Uplink supports XGMII interface for 10-Gigabit * L2 search table supports 32K MAC addresses * Jumbo Frame support (9 KB) Supports * Spanning 4K VLAN address and 802.1s Multiple Tree protocol Supports * queues 802.1p and/or DiffServ with four priority Supports 802.3ad link aggregation * (LACP) and marker protocol control protocol * Supports selected MIB groups in RMON and SMON Supports up to 32K IP multicast * option to cross VLAN boundariesgroups with the Full-duplex and half-duplex operation * 802.3x flow control and backpressure with IEEE * Built in 32-bit, 33-MHz PCI bus interface * Flexible multiplexer modes * Packaged in 785-pin BGA
* Complete switch on a chip integrates 12 10/100/1000
and one 10G Ethernet Media Access Controllers (MACs) supporting RMII, GMII, XGMII and TBI interfaces, including multi-layer forwarding and filtering logic and internal ARL tables and packet buffering. shared by all ports. Multicast MAC addresses, including IP multicast, can also be stored and searched.
* Supports 32K internal MAC addresses, which are
* Supports Quality of Service (QoS). Each output port
* Filters and forwards traffic at full wire speed on all 13 * Provides a mechanism to bundle together up to 12
ports at all layers of functionality. This equates to 44 Gbps of bandwidth. ports at the same speed to form a port bundle or a trunk group, establishing up to six trunk ports.
has four priority queues and their assignment can be based on DiffServ TOS field or the 802.1p priority field.
BCM5632 Switching Solution
Fiber XCVR or BCM5402 GMII/TBI GMII/TBI Fiber XCVR or BCM5402 GMII/TBI GMII/TBI Fiber XCVR or BCM5402 GMII/TBI GMII/TBI
Fiber XCVR
XAUI
BCM8011
XGMII
BCM5632
PCI
CPU Subsystem
System Bus
BCM5632
OVERVIEW
Block Diagram
Output Queueing Shared Buffer Buffer Manager MIB Counters PCI Interface To CPU
Rx FIFO
Tx FIFO
Serial to Parallel
Parallel to Serial
Table Maintenance Port Manager L2 MAC Table
Rx FIFO
Rx FIFO
Rx FIFO
Tx FIFO
Tx FIFO
10 G MAC
The BCM5632 switching processor chip supports 12 Gigabit ports and one 10-Gigabit uplink with all ports in wirespeed operation. The BCM5632 is ideal for applications such as multi-Gigabit port switches or aggregating multiple-Gigabit ports to a 10-Gigabit backplane. For Gigabit ports, the BCM5632 supports PCS (802.3z, 1000BASE-X) or GMII (802.3ab, 1000BASE-T) interfaces with full-duplex operation at Gigabit speed, and full- or halfduplex operation at 10/100 Mbps speed (using 1000BASET). For the uplink port, the BCM5632 supports XGMII. The BCM5632 supports 802.1Q VLAN tagging as an option (Qon). The BCM5632 supports 802.1v VLAN Classification by Protocol. There are four user-programmable protocols that can be set up per port by the VLAN Classification EtherType and the VLAN Priority/TAG registers. The BCM5632 supports both port-based and tagged (802.1q and 802.3ac) Virtual LAN (VLAN). The BCM5632 also supports 4K VLAN addresses with the 802.1s Multiple Spanning Tree option, and flexible and programmable ingress and egress checking rules for VLAN processing.
10 G-Port
Broadcom(R), the pulse logo(R) and Connecting everything(R) are trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners.
BROADCOM CORPORATION 16215 Alton Parkway, P.O. Box 57013 Irvine, California 92619-7013
(c) 2002 by Broadcom Corporation. All rights reserved. 5632-PB03-R-10.31.02
Tx FIFO
G MAC
G MAC
VLAN Table
G-Port
G-Port
The BCM5632 supports Ethernet frames with lengths from 64 bytes to 9 KB. Runt or long frames are dropped at the input port. The minimum inter-packet gap (IPG) is assumed to be 64-bit IDLE plus 32-bit preamble. Packets with shorter than minimum IPG are not dropped, but wirespeed performance is not guaranteed. The BCM5632 also supports 802.3ad port aggregation. The 12Gigabit ports can form up to six trunks, with a maximum of twelve ports in a trunk. The distribution algorithm is user-selectable. The Link Aggregation Control Protocol (LACP) frames are handled by the accompanying CPU and the marker protocol is handled in hardware. The BCM5632 can be initialized and configured by an EEPROM or a CPU, which is also responsible for search table updates and management functions. The CPU is a separate port to the device, containing its own Tx FIFO and Rx FIFO. The device implements a 32-bit, 33-MHz peripheral component interconnect (PCI) for flexible CPU selection and interface. Other features include frame trapping and forwarding to the CPU, port monitoring, and broadcast storm control to reduce broadcast traffic through the switch. The BCM5632 also offers a flexible Multiplexer mode in which the L2 switching functionality can be turned on and off.
(R)
Phone: 949-450-8700 FAX: 949-450-8710 Email: info@broadcom.com Web: www.broadcom.com

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